The stability performance of circuits having feedback is improved by providing compensation so as to increase phase margin. A well known technique for improving phase margin takes advantage of the Miller Effect, by adding a Miller-compensating capacitance in parallel with a gain stage, e.g., the output stage of a two stage amplifier circuit. Such a configuration results in the well-known and desirable phenomenon called pole splitting, which advantageously multiplies the effective capacitance of the physical capacitor employed in the circuit. See, e.g., for background on compensation of amplifier circuits using Miller-compensating capacitance, Paul R. Gray and Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, Third Ed., John Wiley & Sons, Inc., New York, 1993, Ch. 9, especially pp. 607-623.
A problem arises when the load capacitance seen by a circuit having compensating capacitance such as Miller-compensating capacitance becomes large. This requires the compensating capacitance to increase in value in order to maintain stability. However, the larger compensating capacitance occupies more physical space. But, this is not a luxury that can be afforded in an environment where more circuits are integrated onto the same die, which, of course, is the trend.
There is thus a need for a way of dealing with larger load capacitance seen by amplifier circuits having compensating capacitance such as Miller-compensating capacitance, without placing increasing demands on die area for the circuit. There is also a need to optimize and reduce the silicon area requirement of existing circuit designs using such capacitors, to allow greater chip packing densities, and thus single integrated chip solutions.